A common function of transmit and receive stations is to extract a clock signal from the data stream transmitted between the stations and to use the recovered clock signal to properly synchronize the operations performed on the incoming data, e.g., sampling and decoding of the data. In order to use the clock signal, it must be of the same frequency as and as close in phase as possible to the transmitted data stream.
A phase picker clock recovery architecture adjusts the phase of a recovered clock signal in response to a filtered phase error provided by a phase detector. The phase detector compares the phase of the recovered clock signal with the incoming data, generating an error signal representing the phase difference between the signals. The error signal is used to drive an adaptive control loop which seeks to minimize the phase difference by selecting a different phase of N phases of a reference clock signal, provided by a clock generation module (CGM), to be an updated clock signal. The N phases of the reference clock signal generated by the clock generation module are provided by tapping off of an N/2 stage differential voltage controlled oscillator (VCO). The selected phase of the reference clock signal is then used as the recovered clock signal and compared to the data stream to update the error term. An N:1 phase multiplexer having the N phases of the reference signal as inputs is used to perform the actual phase selection.
The loop parameters of a phase picker clock recovery system are independent of PVT (process-voltage-temperature) and the CRM (clock recovery module) is completely digital.
A limitation of such architectures is that a phase picker CRM only works for narrow band clock recovery applications. In some situations, this is not a problem. For example, the ethernet 10BT, 100BX and 1000BX standards are such that a narrow band CRM is adequate. However, the problem with extending a phase picker type CRM to recover clocks for higher frequency protocols, such as 100 mb and 1000 mb ethernet, is that the jitter tolerance is limited by the phase adjust resolution of the phase multiplexer. Simulations using a platform that has been correlated well to silicon show that a phase adjust resolution of 200 ps is required for 100 mb ethernet clock recovery, while a 30 ps phase adjust resolution is required for 1000 mb ethernet. A phase adjust step of 30 ps requires a differential VCO stage of delay under 30 ps at slow PVT. This is impossible to implement on current CMOS processes, where such a delay is on the order of 500 ps.
In the absence of using a phase picker architecture, there are several available methods for enhancing the resolution of a phase multiplexer in order to improve the clock recovery function of a circuit.
Coupled VCOs have been used to enhance the number of phase steps that can be obtained from a single VCO. For example, in "Precise-Delay Generation Using Coupled Oscillators", a dissertation by John Maneatis, Stanford University, June 1994, a method of coupling MN stage ring oscillators is described. The method provides M*N phases of the VCO frequency with a phase difference between adjacent phases enhanced by a factor of M beyond that possible using a single N phase VCO.
Another method involves using an array of delay-locked-loops (DLL). This method is described by J. Christianson, CERN, Geneva, in a publication entitled "An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops." The Christianson method uses M delay-locked-loops of N stages, the inputs for which come from consecutive stages of an M stage delay-locked-loop. This provides a delay resolution of a delay in the N stage phase-locked-loop divided by M.
Another approach to enhancing phase resolution uses a mixer to interpolate between two CGM phases, doubling both the number of phases and the phase adjust resolution. This procedure can be repeated (doubling again), but simulations have shown that beyond two doublings, the precision of the enhanced phase resolution steps degrades.
Finally, an uncompensated interpolation method using inverters with switchable loads to produce an adjustable delay is described by M. Bazes et al. in "An Interpolating Clock Synthesizer", IEEE Journal of Solid-State Circuits, Vol. 31, No. 9, September 1996. This method uses inverters with N switchable loads to create the adjustable delay. The delay interpolator is calibrated by determining how many loads are required to be connected to span one gross phase step. Once this number is determined, the remaining loads are disabled. The number of points in the interpolation change depends upon PVT. For example, for fast PVT, it may take ten loads to span the gross phase step, while at slow PVT, it may take only three. This makes the actual delay step of the interpolator a function of PVT, which is acceptable for a CGM, but it is not acceptable for a CRM, where the phase step resolution is a critical parameter.
What is desired is an apparatus for increasing the phase resolution of the clock signals selected by a phase multiplexer which is part of a clock recovery circuit and which overcomes the limitations of existing devices.